This invention relates generally to a bus and, more particularly, to a video bus for high speed multi-resolution imagers.
A solid state imager is a semiconductor device capable of converting an optical image into an electronic signal. Imagers can be arranged in a matrix and utilized to generate video signals for video cameras, still photography, or anywhere incident radiation needs to be quantified. When incident radiation interacts with a photogate, charge carriers are liberated and can be collected for sensing. The number of carriers collected in a photogate represents the amount of incident light impinging on the site in a given time-period.
There are two basic devices with many variants, employed to collect and sense, charge carriers in a photogate. The two basic devices are photodiodes and photogates. Variants of photodiodes include, but are not limited to: Pinned, P-I-N, Metal-Semiconductor, Heterojunction, and Avalanche. Photogate structures include: Charge Couple Devices (CCD), Charge Injection Devices (CID) and their variants that include virtual phase, buried channel and other variations that utilize selective dopants. The selective dopants are used to control charge collection and transfer underneath and between the photogate(s) and the sense node.
The solid state imagers heretofore used have been dominated by CCD""s because of their low noise as compared to Photodiodes and CIDs. The low noise advantage of CCD imagers is the result of collecting the photon generated charge at the pixel site and then coupling or shifting the actual charge to an amplifier at the periphery of the array. This eliminates the need for the long polysilicon and metal busses that degrade the signal with their associated resistance and capacitance. However, the low noise of the CCD requires the imager to be read in a fixed format and once the charge is read it is destroyed. The requirement of coupling the collected photon charge from the pixel to the periphery amplifier (a.k.a. CTE), requires proprietary processing steps not compatible with industry standards CMOS or BiCMOS processes.
Solid state imaging devices have developed in parallel with CMOS technology and as a result all imager manufacturers developed their own proprietary processes to maximize imager performance characteristics and wafer yield. Specialized silicon wafer processing kept imager prices relatively high. Linear active pixel sensors have been commercially produced since 1986. Beginning in the early 90""s the move to transfer the proprietary processes to an industry standard CMOS processes was on. The advantages of using an industry standard process include: competitive wafer processing pricing, and the ability to provide on chip timing, control and processing electronics. By the end of the year 1992, a 612xc3x97512 CMOS compatible, CID imager with a preamplifier and CDS per column had been fabricated. The imager could either be operated as a random access 512xc3x97512 CID, or all the columns could be summed together and operated as a linear active pixel sensor.
Area arrays utilizing active pixel sensors in which a photodiode or photogate is coupled to an output source follower amplifier which in turn drives a Correlated Double Sampling (CDS) circuit, where the two outputs of the CDS cell then drives two more source followers circuits that in turn are fed into a differential amplifier are shown in U.S. Pat. No. 5,471,515 which is herein incorporated by reference. This uses source follower circuits, that typically have gains less than unity that vary from one source follower to another. The source follower gain variation is due to variations of FET thresholds. The source follower gain variation results in a pixel to pixel gain mismatch. Also, the active pixel sensors suffer gain variations due to the CDS circuit per column, when the CDS employs a source follower pair to drive its output. The resulting CDS signal and its corresponding offset can have different gains that are not correctable by the differential amplifier. Also, the source follower configuration of active pixel doesn""t allow for binning of pixels.
The voltage mode of operation of prior art does not allow for binning, which, is the summation to two or more pixel signals at once.
What is needed is an imager which has the low noise level of a CCD, the random access, and binning of a CID, and uniform gain and response from all pixels; while, maintaining low power, ease of use and high analog video frame rates.
In addition to finding an imager which has the low noise level of a CCD, the random access, and binning of a CID, and uniform gain and response from all pixels, imagers suitable for industrial and/or scientific applications are also needed. Over the last 30 years the CCD sensor and camera electronics technology has evolved to meet most of the demands for industrial and/or scientific applications. However, the resulting cameras require a state-of-the-art, large pixel, multi-port CCD chip plus several extra chips and usually several circuit boards filled with electronics to accomplish this. Thus, the cameras cannot physically fit in certain applications, the power consumed is significant, and the resulting cameras are far too expensive for many applications. The necessary recombination of the video data from several ports, further increases the video processing complexity and ultimately drives-up the cost and size of the video system.
As discussed earlier over the past several years, thanks to design rule shrinkage, image sensors using sub-micron CMOS process technology have become practical. By using CMOS technology for the sensor array itself, the problem of integrating extra circuitry on chip becomes straightforward. Elements such as A/D converters, timing generators, control circuitry and interface circuitry can easily be added. In addition, the operation of CMOS imagers is simplified by the elimination of the need for precise timing and level control of multiple clocks required to drive the large capacitance transfer gates inherent in CCD""S. Even with all of these factors, including the exceptional speed and pico-second gate delays of sub-micron processes, the analog video bandwidth per port has not changed much over the past twenty years.
Active pixel sensors (APS) have been proposed as the means to achieve the flexible benefits of CMOS cameras on a chip. Unfortunately, there are performance issues with the fundamental APS approach that limit its performance and functionality. While these limitations may be acceptable for low-end consumer imaging applications, the demands of scientific, professional and industrial applications have, up until now, been largely unmet by CMOS image sensors.
More specifically, industrial and scientific imaging applications require much higher performance and functionality than that required for low-end consumer imaging products. Many of the applications require high readout speeds for video rate or even faster imaging without sacrificing image quality. In addition to image quality, the applications have come to demand greater functionality in the camera. Features such as flexible shuttering and electronic zoom, random access and selectable region of interest for maximizing frame rates and minimizing data storage (especially useful in tracking applications). Lowering the cost of machine system development is the recent advancement of single chip CMOS cameras. Newly developed CMOS cameras have all the flexibility previously listed, however the analog video bandwidth per port has not changed from the traditional CCD, CID or Photodiode technologies.
Most mega-pixel image sensors, including both CCD imagers and APS imagers, have a maximum pixel rate inadequate to meet the frame rate needs of industrial and scientific imaging. CCD devices are limited by both clocking rates and the speeds of the Correlated Double Sampled (CDS) circuitry. In addition the higher amplifier bandwidth required for higher pixel rates increases noise levels. With the column parallel nature of CMOS imagers, the amplifier and CDS can be run at the line rate rather than the pixel rate. The video bandwidth constraints come in terms of the multiplexing speed. CMOS imagers typically multiplex their signals onto a common analog video bus. The more signals that are multiplexed or switched onto the bus, the greater the capacitive load of that bus. Therefore, as more signals are connected to the bus, the bandwidth of the bus is reduced. Alternatively, greater power is needed to charge and discharge the bus with its associated capacitance to maintain bandwidth. This traditional bus structure described above involves N signals that are switched onto one bus.
One example of a CMOS imager 98 with column parallel amplifiers 100 that drive a common video bus 102 is illustrated in FIG. 5. In this example, the common video bus 102 is seen mostly as a capacitive load 140 to each individual column amplifier 100. In order for each amplifier 100 to truly represent the pixel value onto the common video bus 102, each amplifier 100 must charge or discharge the bus 102 with in one pixel time constant. The pixel value signal must be stable long enough for a sample and hold circuit (or similar) to accurately present the resultant signal to an A to D converter (not shown). Typically, at least 5xcfx84 (tau or time constants) is desired to accurately allow the video bus 102 to settle the video value presented by each individual column amplifier 100, although this can vary between applications. At higher video bus speeds each amplifier 100 is unable to properly charge or discharge the video bus 102 resulting in a loss of contrast ratio. At higher pixel element rates where the contrast ratio is compromised, the individual column amplifier characteristic and the video switch characteristics begin to affect the resultant video. Each individual column amplifiers 140 has a slightly different offsets with slightly different drive capabilities and each video switch 120 will have slightly different resistances and slightly different thresholds. This combination of column amplifier and video switch characteristics results in each column amplifier 100 having different time constants relative to charging and discharging the video bus 102. The column amplifier 100 and video switch 120 are common to every pixel in that column. Thus, variations in the video switch characteristics result in what appears to be column based Fixed Pattern Noise (FPN). As more columns are added, each video switch 120 adds more associated capacitance 140 due to the source and drain junctions of MOSFET or Bipolar transistors. The more columns added to the bus 102, the higher the total capacitance.
In order to overcome these constraints, one prior solution by designers of CCD""s and APS sensors has been to divide up the imager into halves, quarters, or smaller groupings of sub-imagers jammed together. One example of this prior design solution is shown in FIG. 6. In this example, the imager 80 is divided up it to four sub-imagers 80(1)-80(4). The signal from each of these sub-imagers 80(1)-80(4) is brought out to its own port 82(1)-82(4). This structure or architecture also involves getting many signal streams of N signals on to one bus. This design has been used to provide high frame rate devices and to meet standard frame rates with large mega-pixel imagers. Unfortunately, this design adds system size, complexity, power and cost to handle the multiple analog amplifier chains. Additionally, it is an extremely challenging task to balance the amplifier chains completely over all possible pixel rates and temperatures. This issue has become even more of a problem in recent years as imagers have grown larger, now up to full wafer size. The process variations across an array can lead to further balance problems, and even variations in noise characteristics due to process variations across a wafer.
A bus system for transferring signals from a plurality of signal streams to an output in accordance with one embodiment of the present invention includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before selecting the signals to the output multiplexor.
An imager in accordance with another embodiment of the present invention includes a plurality of streams of signals, a plurality of signal buses in parallel, an output, and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses (i.e. an input multiplexor) and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output multiplexor.
A bus system for transferring signals from a plurality of signal streams to an output in accordance with another embodiment of the present invention includes a plurality of signal buses coupled to the plurality signal streams, a plurality of first switches, a plurality of second switches, and a control system. Each of the plurality of first switches is coupled between one of the plurality of signal streams and one of the plurality of signal buses. Each of the plurality of second switches coupled between one of the plurality of signal buses and the output. The control system is coupled to the first and second switches and closes two or more of the plurality of first switches to couple signals from the two or more of the plurality of signal streams to two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before closing one or more of the plurality of second switches of the output multiplexor to couple the signals to the output. In other words, this system described above involves N signals multiplexed to two or more busses (or M busses) and then multiplexed on to one bus or in other words a two stage multiplexor with an input multiplexor and an output multiplexor. A two stage multiplexing system allows for a variety of different operations, such as allowing signal or pixel signal skipping and allowing multiple signals or pixels signals to be selected at once. By way of example, pixel signals could be alternately individually selected and then two adjacent signals could be selected to allow signal averaging or interpolation, effectively changing the native resolution of pixel for either higher or lower resolution. This present invention coupled with Active Column Technology as described in U.S. Pat. No. 6,084,229, which is herein incorporated by reference, allows for binning or skiping of pixels along the rows as well as the columns.
A method for transferring signals in accordance with yet another embodiment of the present invention includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses also known as input multiplexing before demultiplexing select signals by the output multiplexor. Also, included in this particular embodiment is a reordering multiplexor that redirects signals from the output multiplexor to one or more outputs.